1. Field of the Invention
The present invention relates to a semiconductor integrated circuit provided with a protection circuit against electrostatic breakdown of a gate oxide which is caused by plasma etching or the like in the process of fabricating the semiconductor integrated circuit, and to a layout design method therefor.
2. Description of the Prior Art
FIG. 27 is a sectional view of a part of a pMOS transistor. In FIG. 27, reference character 10 denotes a p-type substrate; 11, an n-type well; 12, gate oxide; 13, gate polysilicon; 14, a insulator; 15, a contact hole; 16, interconnection metal; 17, field oxide; and 18, a photoresist.
In the process of fabricating a semiconductor integrated circuit, when the interconnection metal pattern 16 is formed by plasma etching or plasma ashing, charge passes through the interconnection metal 16 and accumulates in the gate polysilicon 13 due to the charge in the plasma. The smaller the components of semiconductor integrated circuit, the thinner the gate oxide 12, and thereby the lower its insulation strength. If the voltage between the gate polysilicon 13 and an n-type well 11 exceeds the insulation breakdown voltage due to the accumulation of charge, a discharge occurs between the gate polysilicon 13 and the n-type well 11 with damaging the gate oxide 12, thereby changing the characteristics of the transistor, such as the threshold voltage and the drain current thereof. This prevents the normal circuit operation. This phenomenon becomes more serious as the interconnection length is increased by multilayer wiring.
In order to solve this problem, a diode with a reverse breakdown voltage which is lower than the insulation breakdown voltage of the gate oxide 12 and higher than the supply voltage is connected between the gate and the substrate, as shown in FIGS. 28A, 28B and 29. FIG. 28B is a sectional view taken along line B--B in FIG. 28A, and FIG. 29 is a circuit diagram of the structure shown in FIG. 28A and 28B.
In FIGS. 28A and 28B, reference character 19 denotes an n.sup.+ -type region; 20, a contact hole; 21S and 21D each, a p.sup.+ -type region; 22S and 22D each, an n.sup.+ -type region; 23, interconnection metal; 24, power supply metal line for supplying a potential higher than the ground; and 25, ground metal line as another power supply line. A pMOS transistor TP comprises the p.sup.+ -type regions 21S and 21D, the gate polysilicon 13 and the gate oxide 12. A nMOS transistor TN comprises the n.sup.+ -type regions 22S and 22D, the gate polysilicon 13 and the gate oxide 12. The diode D comprises the p-type substrate 10 and the n.sup.+ -type region 19 with forming a pn junction.
The above-described structure causes the accumulated charge to pass through the diode D and flow into the substrate before the gate oxide is electrostatically broken down if charge is accumulated in the gate polysilicon 13 in the process of fabricating IC. The diode D may be connected, as shown by a dotted line in FIG. 29.
However, when the diode D is arranged for each gate, as shown in FIG. 28A, excess region is required for the diodes D, and the chip size is thus increased. In particular, in ASIC of a gate array, a standard cell system or the like, since basic cell circuits are arranged in a matrix, an increase in the size of the basic cell circuits including the diodes D significantly affects an increase in the chip size. In addition, when the diode D is arranged for each gate, the number of the diodes D becomes excessively large, and the operating speed of the circuit is thus decreased due to the parasitic capacitance of each diode.
On the other hand, when the diodes D are connected to only the gates to which long wiring causing the problem of electrostatic breakdown is connected, since excess region must be secured for the diodes, the design becomes complicated.